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ADE7854/ADE7858/ADE7868/ADE7878
Table 51. CONSEL[1:0] Bits in Energy Registers
Data Sheet
Energy Registers
AWATTHR, AFWATTHR
BWATTHR, BFWATTHR
CONSEL[1:0] = 00
VA × IA
VB × IB
CONSEL[1:0] = 01
VA × IA
0
CONSEL[1:0] = 10
VA × IA
VB = ?VA ? VC
CONSEL[1:0] = 11
VA × IA
VB = ?VA
VB × IB
VB × IB
CWATTHR, CFWATTHR
AVARHR, AFVARHR
BVARHR, BFVARHR
VC × IC
VA × IA’
VB × IB’
VC × IC
VA × IA’
0
VC × IC
VA × IA’
VB = ?VA ? VC
VC × IC
VA × IA’
VB = ?VA
VB × IB’
VB × IB’
CVARHR, CFVARHR
AVAHR
BVAHR
CVAHR
VC × IC’
VA rms × IA rms
VB rms × IB rms
VC rms × IC rms
VC × IC’
VA rms × IA rms
0
VC rms × IC rms
VC × IC’
VA rms × IA rms
VB rms × IB rms
VC rms × IC rms
VC × IC’
VA rms × IA rms
VB rms × IB rms
VC rms × IC rms
Table 52. LCYCMODE Register (Address 0xE702)
Bit
Location
0
Bit Mnemonic
LWATT
Default Value
0
Description
0: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,
BFWATTHR, and CFWATTHR) are placed in regular accumulation mode.
1: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,
BFWATTHR, and CFWATTHR) are placed into line cycle accumulation mode.
1
LVAR
0
0: the var-hour accumulation registers (AVARHR, BVARHR, and CVARHR) are placed in regular
1: the var-hour accumulation registers (AVARHR, BVARHR, and CVARHR) are placed into line-
cycle accumulation mode.
2
LVA
0
0: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are placed in regular
accumulation mode.
1: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are placed into line-cycle
accumulation mode.
3
ZXSEL[0]
1
0: Phase A is not selected for zero-crossings counts in the line cycle accumulation mode.
1: Phase A is selected for zero-crossings counts in the line cycle accumulation mode. If more
than one phase is selected for zero-crossing detection, the accumulation time is shortened
accordingly.
4
ZXSEL[1]
1
0: Phase B is not selected for zero-crossings counts in the line cycle accumulation mode.
1: Phase B is selected for zero-crossings counts in the line cycle accumulation mode.
5
ZXSEL[2]
1
0: Phase C is not selected for zero-crossings counts in the line cycle accumulation mode.
1: Phase C is selected for zero-crossings counts in the line cycle accumulation mode.
6
RSTREAD
1
0: read-with-reset of all energy registers is disabled. Clear this bit to 0 when Bits[2:0] (LWATT,
LVAR, and LVA) are set to 1.
1: enables read-with-reset of all xWATTHR, xVARHR, xVAHR, xFWATTHR, and xFVARHR
registers. This means a read of those registers resets them to 0.
7
Reserved
0
Reserved. This bit does not manage any functionality.
Table 53. HSDC_CFG Register (Address 0xE706)
Bit
Location
0
Bit Mnemonic
HCLK
Default Value
0
Description
0: HSCLK is 8 MHz.
1: HSCLK is 4 MHz.
1
HSIZE
0
0: HSDC transmits the 32-bit registers in 32-bit packages, most significant bit first.
1: HSDC transmits the 32-bit registers in 8-bit packages, most significant bit first.
2
HGAP
0
0: no gap is introduced between packages.
1: a gap of seven HCLK cycles is introduced between packages.
Rev. H| Page 96 of 100
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